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ada4355: Add idelay calibration functionality #1690

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Merged
merged 3 commits into from
May 8, 2025
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PIoandan
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@PIoandan PIoandan commented Apr 29, 2025

PR Description

Detect when it is encountering a frame or data error.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

Detect when it is encounter a frame or data error.

Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
@sarpadi
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sarpadi commented May 5, 2025

Register map updates should come with documentation updates

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PIoandan commented May 5, 2025

Register map updates should come with documentation updates

Done.

Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
@PIoandan PIoandan requested a review from IuliaCMoldovan May 7, 2025 06:46
IuliaCMoldovan
IuliaCMoldovan previously approved these changes May 7, 2025
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Checked the doc and regmap and they look ok

Comment on lines 77 to 90
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr)
7'h32: up_rdata <= {29'd0, up_enable_error};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
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fix indentation

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Done.

// processor write interface

always @(posedge up_clk) begin
if (up_rstn == 0) begin
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indentation (hopefully it's not a TAB)

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Fix it.

@@ -351,6 +385,9 @@ module axi_ada4355_if #(
RESET : begin
shift_cnt <= 0;
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indentation

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Done.

reg frame_err_r;
reg data_err_lane_0_r;
reg data_err_lane_1_r;
reg [15:0] lane_0_mask = 16'h5555;
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these should be localparam, not reg

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Done.

@@ -120,6 +124,7 @@ module axi_ada4355_if #(
reg [ 1:0] serdes_valid = 2'b00;
reg [ 1:0] serdes_valid_d = 2'b00;
reg [ 2:0] shift_cnt = 3'd0;
reg [ 4:0] delay = 5'd0;
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you have a mix of "d", 'h" and "b" types. please use only one (preferably "h")

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Done.

@@ -275,38 +286,40 @@ module axi_ada4355_if #(
end
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fix indentation (284)

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Done.

Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
@PIoandan PIoandan merged commit 55afbcc into main May 8, 2025
3 of 4 checks passed
@PIoandan PIoandan deleted the ada4355_idelay branch May 8, 2025 11:37
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3 participants